Wafer probing is one of several testing operations performed throughout the manufacture of semiconductor devices. Prior to packaging the individual semiconductor die and while still in the wafer form, each die is probed on a tester. Traditional wafer probing methods utilize probe cards which are adapted to the particular tester being used. The probe cards typically employ a plurality of cantilever probe needles which are arranged in a peripheral configuration that matches the bond pads configured on each semiconductor die. The probe needles are placed in contact with the bond pads of each die and diagnostic testing is performed. After the completion of testing on one die, the wafer is moved so that testing can be performed on an adjacent die. The process is reiterated until all die on the wafer have been tested.
As semiconductor device performance increases, generally so too does the number of input and output connections required to operate each device. For each input and output terminal there is a corresponding bond pad on each semiconductor die. Traditionally, these bond pads are located around the periphery of the die. As the number of bond pads around the semiconductor die increases due to the need for a higher number of input and output terminals, the total area of the semiconductor die is increased. Often, a die size is considered to be "bond pad limited" because the size of the die is dictated by the number of bond pads about the periphery and by the required spacing between adjacent pads. The bulk of the circuitry for an individual die may consume an area smaller than the actual die size, but the need for a minimal bond pad spacing about the periphery will require that the die size be made larger than the bulk of the circuitry to accommodate all the bond pads. Because semiconductor manufacturers are continually being driven by market demand to minimize die size, bond pad spacing limitations are a serious impediment to having competitive products.
One method to avoid a semiconductor die from being peripherally bond pad limited is to arrange pads of a die in an array configuration over the die surface. Semiconductor die which include pad array configurations are typically packaged using a flip chip method, as compared to peripheral bond pad configurations which are typically either wire-bonded or TAB (tape automated bonding) bonded to a lead frame, tape, or substrate. In a flip chip method, the active surface of a die is mounted (active side down) to a package substrate such that the array of pads on the die is electrically connected to and aligned with a matching array of pads of the substrate. To insure proper connection between the pads on the die and-the pads on the package substrate, conductive bumps may be formed on the pads of the semiconductor die. One type of bump is a controlled collapse chip connection (C4). The bumps resulting from such a method are often called C4 bumps. C4 bumps are typically formed at the wafer level so that the C4 bumps are present on each die during the wafer probing process. Unfortunately, conventional cantilever probe needles and cantilever probe cards cannot be used to probe all arrayed C4 bumped wafers. Because the C4 bumps are in an array configuration on the die surface, wherein the bumps can be several rows deep, it is difficult to develop a probe card in which cantilever probe needles can successfully probe all bumps at the same time. Furthermore, cantilever probes will occasionally damage the C4 bumps during probing.
A technique has been developed to probe bumped wafers which dispenses with the need to use traditional cantilever probe needles. The alternative technique is called an array probe. With an array probe, traditional cantilever probe needles in a peripheral configuration are replaced with probe wires in an array configuration which match the configuration of the bumps on each die. A difficulty with the use of an array probe is that the probe wires must somehow be connected to conductive traces on a probe card in order for the wafer probing to be successful in conventional testers. At present, the mechanism to achieve the proper connections between the probe wires and the probe card is through a tedious manual or hand wiring process. Each probe wire is connected to a corresponding conductive trace on the tester probe card by a "jumper wire". The jumper wires are manually connected between the probe wires and the probe cards, making the resulting product quite expensive. Moreover, the lead time required to make this probe array assembly is quite long due to the high number of connections required in a typical C4 application and due to the manual manner in which such connections are made.